1. Field of the Invention
The present invention relates to a clock generator capable of performing operation accurately and being freedom from noise effects, and may be controlled at a low voltage.
2. Description of the Prior Art
A PLL (a phase Locked Loop) has been widely used in many electrical fields. The PLL is a circuit to output multiple clock signals in synchronization with an input clock signal.
Recent microprocessors operate in a higher operation frequency, for example, in a higher clock of several hundreds MHz, so that incorporating of the PLL is indispensable to the microprocessors.
The type of conventional PLLs is an analogue type to control an oscillating frequency by controlling the voltage of a capacitor to store an control voltage of a Voltage Control Oscillator (VCO) based on a charge pump.
However, it is difficult to operate the conventional analogue type PLL under a low voltage and noises greatly affect on the operation of the conventional PLL. Furthermore, it takes many times for the conventional PLL to reach a stable state and the PLL stops the oscillation when once the supply of the input clock is halted and it take a long time period to restart the operation of the PLL.
In order to eliminate and to solve the drawbacks or the problems described above, conventional techniques provided various methods. For example, the following conventional literature 1 discloses a frequency multiplier generator using digital delay lines.
Literature 1: "A Portable Clock Multiplier generator Using Digital CMOS Standard Cells", Michel Combes, Karim Dioury, and Alain Greiner, IEEE Journal of Solid State Circuits, Vol. 31, No. 7, July, 1996.
FIG. 8 is a block diagram showing the configuration of a conventional frequency multiplier. In FIG. 8, the reference number 1 designates a flip flop circuit, 2 denotes a divider, 3 indicates a comparator, 4 designates a control circuit, and 6 and 7 indicate delay circuits, respectively. FIG. 9 is a timing chart showing the operation of the conventional frequency multiplier 10 shown in FIG. 8.
Next, a description will now be given of the operation of the conventional frequency multiple circuit.
In the operation of the conventional frequency multiple circuit 10, there is a possibility to enter a state that the F/F circuit outputs no pulse under the initial state of a delay time of both the delay circuits 6 and 7 as the digital delay line during one period of the timing T1 to the timing T2, as shown in the timing chart of FIG. 9. In this case, there is a drawback that the F/F 1 outputs no multiplied output signal accurately during the one period from the timing T1 to the timing T2 of the input clock shown in FIG. 9 because the output signal M of the divider 2 is asserted during this one period based on a difference between a delay time from the rising edge (Timing T1) of the input clock to the time to negate the output signal M of the divider 2 and a delay time from a falling edge (Timing T1) in the fourth pulse of the multiplied clock output signal as the output signal of the F/F 1 to a time to assert the output signal M of the divider 2.
In addition, the literature 1 showing the frequency multiple circuit 10 as the conventional technique described above has described no phase lock between the input clock and the output signal M of the divider 2. Therefore the literature 1 provides the PLL having an insufficient function.
On the other hand, there is a conventional technique that is obtained by combining a phase locked circuit with the frequency multiple circuit 10 using the digital delay line shown in FIG. 8.
FIG. 10 is a block diagram showing a conventional clock generation circuit 15 that is obtained by combining the phase locked circuit with the frequency multiple circuit 10 using the digital delay line shown in FIG. 8. In FIG. 10, the reference number 10 designates the frequency multiple circuit shown in FIG. 8, 11 denotes a phase locked circuit, 12 indicates a digital delay line forming the phase locked circuit 11, 13 designates a digital counter, and 14 denotes a comparator.
Next, the operation of the conventional clock generation circuit will be explained.
The multiplied clock output signal (or an output clock) provided from the frequency multiple circuit 10 is inputted into the digital delay line 12 in the phase locked circuit 11, then the digital delay line 12 outputs a PLL output signal to outside. The comparator 14 compares the phase of the PLL output signal with the phase of the input clock, and outputs the comparison result to the digital delay line 12 as a feedback signal in order to adjust a delay between both the input clock and the PLL output signal and to coincide the input clock with the PLL output signal in phase.
However, the conventional clock generation circuit 15 having the configuration shown in FIG. 10 has a drawback in which a compensation ability to compensate a delay of the PLL output signal caused by the influence of a voltage value, a temperature value, and so on becomes bad, because it takes many times to reflect the compensation of the period and the phase based on the comparison result obtained by the comparator 3 in the frequency multiple circuit 10 or the comparator 14 in the phase locked circuit 11 when the delay time of the digital delay line 12 becomes longer than the period of the input clock, for example.
FIG. 11 is a timing chart showing the operation of the conventional clock generation circuit 15 shown in FIG. 10. As shown in the timing chart of FIG. 11, when the delay time of the digital delay line 12 in the conventional clock generator 15 is locked in the delay time of twice of the period of the input clock, the comparison result that has been output at the timing T1 from the comparator 3 incorporated in the frequency multiple circuit 10 is output firstly by the phase locked circuit 11 as the PLL output signal only after two periods of the input clock counted from the timing T4. This causes the possibility to decrease the compensation ability and to happen that the delay compensation operation process can not be executed correctly because an incorrect PLL output signal will be generated at the timing T5.
FIG. 12 is a block diagram showing the configuration of the conventional digital delay line 12. In FIG. 12, the reference number 17 indicates a plurality of delay elements forming the digital delay line 12, 18 indicates a selector to select one of the plurality of delay elements 17.
For example, in the techniques disclosed in the literature 1 described above and the following literature 2, the selector 18 selects one of the delay elements 17 in order to adjust the delay time.
Literature 2s: "Multifrequency Zero-Jitter Delay-Locked Loop"; Avner Efendovich, et al., IEEE Journal of Solid-State Circuits, Vol. 19, No. 1, January, 1994.
However, it must be required in the conventional digital delay line having this configuration to switch the entire delay elements 17 even if a delay time of the digital delay line is shorter. This causes to consume un-required electric power.
FIG. 13 is a diagram showing the configuration of another conventional digital delay line. As shown in FIG. 13, the position of an input terminal is changed by using control signals "a" and "b" so that each delay element is selectively activated in order to obtain a desired delay time and also to reduce the power consumption of the digital delay line. However, there is a drawback in the configuration of the digital delay line shown in FIG. 13. For example, when a counter value is changed while the clock generation circuit is operating, namely, when the position of the input terminal is shifted from the node "a" to the node "b", there is a drawback that unstable electric potential is added on the output "a" at the timing T8 shown in FIG. 14.
As described above, there is the drawback that in the digital PLL using the digital delay line incorporated in the conventional clock generation circuit, a following phase comparison is performed before the change of the delay time of the digital delay line is reflected to the PLL output signal under an initial state of the multiplied clock output signal as the output signal of the frequency multiple circuit 10, so that the compensation ability to the change of the temperature and the voltage becomes reduced and it becomes difficult to perform the phase lock operation. Furthermore, when all of the delay elements in the digital delay line are switched, the conventional clock generation circuit consumes un-necessary power consumption. Moreover, in the case that the input position of the digital delay line is shifted in order to avoid this un-necessary power consumption, it is difficult to lock the phase accurately when the counter value is changed because a hazard is generated on the output of the digital delay line.